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14th International Test Synthesis Workshop (ITSW 2008)
April 7-9, 2008

University of California
Santa Barbara, California, USA

http://www.tttc-itsw.org

CALL FOR PAPERS
Scope -- Author Information -- Committees

Scope

Theme: At-Speed Scan: Challenges and Opportunities

Since the inception of ITSW in Santa Barbara in 1994 chip geometries have shrunk from 500 to 65 nanometers with 45 nanometers on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools and methodologies in all aspects of digital chip design and manufacturing. The widespread use of all aspects of Test Synthesis coupled with powerful pre-silicon verification approaches has been able to keep up with increasing chip complexity.

This year’s workshop will focus on at-speed scan tests, looking at various issues like hardware support, yield loss, test power, defect coverage, pseudo-functional tests and explore whether it is possible to replace functional delay tests with at-speed scan and still maintain product quality. As always, ITSW is open to all submissions in the area of test, including, but not limited, to the following:
  • Register Transfer Level DFT
  • High-Level/Behavioral Test Synthesis
  • System-on-a-Chip (SoC) DFT
  • Memory and Logic BIST
  • Test Synthesis for Debug and Diagnosis
  • DFT for Mixed-Signal Circuits
  • Test Resource Partitioning
  • Functional Verification
  • Power and Noise-Aware Test
  • Design for Reliability
  • High-speed I/O test
  • Reducing the Cost of Test
  • Design for Manufacturing and Yield
  • Board and System Test
  • SER / Concurrent Error Detection
  • Test Synthesis for Reconfigurable Logic

For more information, please refer to the web site: http://www.tttc-itsw.org.

Author Information

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To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format by January 9, 2008.  Acceptance notifications will be sent out on February 27, 2008. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.

For general information, contact:

Nilanjan Mukherjee, General Chair
Mentor Graphics Corporation
Wilsonville, OR 97070
Phone: +1 (503) 685-1721
Fax: +1 (503) 685-4729
Email: GeneralChair@tttc-itsw.org

Submit extended abstracts via email to:

Nur Touba
Electrical and Computer Engineering
University of Texas, Austin, TX
Phone: +1 (512) 232-1456
Fax: +1 (512) 471-5532

Email:ProgramChair@tttc-itsw.org

Committees

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General Chair
N. Mukherjee – Mentor G.

Past General Chair
S. Patil – Intel

Vice Chair
J. Dworak – Brown U.

Program Co-Chairs
N. Touba – U. Texas, Austin
S. Chakravarty - LSI

Panels Chair
V. Chickermane – Cadence

Publicity Chair
A. Jas – Intel

Finance Chair
C. Barnhart – Silicon Aid

Local Arrangements Chair
L. C. Wang – UC SB

European Liaison
M. Zwolinski – U. Southampton

Asian Liaison
C. W. Wu – Nat. Tsing Hua U.

Program Committee
M. Abadir – FreeScale
R. Aitken – ARM
K. Balakrishnan – AMD
S. Blanton – CMU
D. Burek – Magma
K. Chakrabarty – Duke U.
K.-T.Cheng – UC SB
A. Crouch – Inovys
R. Datta – TI
S. Davidson – Sun Micro.
C. Dixit – LSI
D. Goswami – Synopsys
A. Guettaf – Broadcom
M. Hsiao – Virginia Tech.
K. Iwasaki – Tokyo Metro. U.
R. Kapur – Synopsys
M. Laisne – QualComm
K.-J. Lee – Nat. Cheng-Kung U.
A. Majumdar – Sun Micro.
S. Mitra - Stanford
K. Mohanram - Rice U. Texas
M. Nourani –U. Texas, Dallas
A. Orailoglu – UC San Diego
B. Pouya – Freescale
J.  Qian – Cisco
J. Rajski – Mentor Graphics
S. M. Reddy – U. Iowa
M. Tahoori – Northeastern U.
S. Tragoudas – S. Illinois U.
H. Walker – Texas A&M U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 15th International Test Synthesis Workshop (ITSW 2008) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TTTC 2ND VICE CHAIR
Joan FIGUERAS
Universitat Politècnica de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

FINANCE
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

DESIGN & TEST MAGAZINE
Tim CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG

Lucent Technologies
- USA
Tel. +1-732-949-5539
E-mail chenhuan@lucent.com

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Institute of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal University of Rio Grande do Sul - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

INTERNATIONAL TEST CONFERENCE
Jill E. SIBERT
Raspberry Comm.
- USA
Tel. +1-484-894-1111
E-mail jill_sibert@raspberrycom.com

TEST WEEK COORDINATION
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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